//ram_rw模块

module ram_rw(
	input				sys_clk		,
	input				sys_rst_n	,
	
	output				ram_wr_en	,	//ram读使能
	output				ram_rd_en	,	//ram写使能
	output	reg[4:0]	ram_addr	,	//ram读写地址
	output	reg[7:0]	ram_wr_data	,	//ram写数据
	
	input		[7:0]	ram_rd_data		//ram读数据
	);
	
//reg define
reg	[5:0]	rw_cnt;						//读写控制计数

assign	ram_wr_en = ((rw_cnt >= 6'd0) && (rw_cnt <=6'd31))	?	1'b1 : 1'b0;
assign	ram_rd_en = ((rw_cnt >= 6'd32) && (rw_cnt <=6'd63))	?	1'b1 : 1'b0;


//读写控制计数器 技术范围位0~63
always @(posedge sys_clk or negedge sys_rst_n)	begin
	if(!sys_rst_n)
		rw_cnt <= 6'b0;
	else if(rw_cnt ==  6'd63)
		rw_cnt <= 6'b0;
	else
		rw_cnt <= rw_cnt + 6'b1;
end

//读写控制器技术范围：0~31 产生ram写使能 信号和写数据信号
always @(posedge sys_clk or negedge sys_rst_n)	begin
	if(!sys_rst_n)
		ram_wr_data <= 6'b0;
	else if(rw_cnt >= 6'd0 && rw_cnt <= 6'd31)
		ram_wr_data <= ram_wr_data + 8'd1;
	else
		ram_wr_data <= 8'b0;
end

//读写地址信号的 范围：0~31
always @(posedge sys_clk or negedge sys_rst_n)	begin
	if(!sys_rst_n)
		ram_addr <= 5'b0;
	else if(ram_addr == 5'd31)
		ram_addr <= 5'b0; 
	else
		ram_addr <= ram_addr+ 1'b1; 
end

endmodule